Clock signals are used in virtually every IC and electronic system to control timing. For example, every time there is a rising edge on a clock signal, all the flip-flops in a circuit may change state. Frequently, both edges (rising and falling) of the clock signal are used. For example, in a Master-Slave flip-flop, data is read into the flip-flop on one edge of the clock signal, and then appears at the output terminal of the flip-flop on the other edge. Since the Master-Slave flip-flop is performing logic functions during each half of the clock cycle, the two states of the clock (high and low) are preferably each of approximately equal length. (This condition is called a "50% duty cycle".) If one state is appreciably longer than the other, the clock signal is "unsymmetrical" (e.g., the clock signal is low longer than it is high). This limitation is not uncommon; for example, duty cycles of about 10% (i.e., 10% high, 90% low) are often seen. Under these conditions, the frequency at which a circuit can operate may be limited by the length of the shorter state (e.g., by the length of time that the clock signal is high). Therefore, the circuit operates at an unnecessarily low frequency.
To overcome this limitation, circuit designers can extract a 50% duty cycle clock from an unsymmetrical clock signal using a phase-lock loop (PLL) circuit. However, a PLL circuit consumes a great deal of silicon area. Additionally, PLLs are often analog in nature and take an extremely long time to simulate, and a design that works in one manufacturing process may stop working when manufactured using another process. Therefore, PLLs are very difficult to design, and often are not feasible in a given circuit or system. Therefore, duty cycle correction is often not possible using known circuits and methods.
Therefore, it is desirable to provide a duty cycle correction circuit and method that enables a circuit designer to correct an unsymmetrical clock to a 50% duty cycle, using a fairly simple circuit that consumes a relatively small amount of silicon area.